Question 1: Nehalem is the microarchitecture of the first generation of Intel Core i7 processor. It consists of 2, 4, or 8 cores, each with a 64 KB of L1 cache per core (32 KB L1 instruction cache and 32 KB L1 data cache, both with 256-bit cache blocks), a unified 256 KB 8-way set associative L2 cache (with 64-byte blocks) per core, and a shared 8MB 16-way set associative L3 cache (with 64-byte blocks). The 4-way associative L1 instruction cache latency is 3 CPU cycles, while the 8-way associative L1 data cache latency is 4 cycles. The L2 cache access time is 10 cycles, and L3 is 40 cycles. It has a 36-bit address bus