1.Suppose we have the following MIPS assembly code to run:
add $s1, $zero, 16
add $s2, $zero, 32
loop: lw $t0, -16($s1)
lw $t1, -8($s1)
add $t2, $t0, $t1
add $s1, $s1, 8
bne $s1, $s2, loop
| add | lw | bne |
| 1 | 6 | 1 |
For each instruction, suppose we have the following latency in cycles:
1.1.How many cycles are needed until the exit of the loop from the beginning of the code, i.e., “add $s2, $zero, 24” in the following computer architecture.
-Assumption1: An instruction is fetched in 1 clock cycle, but not user data. Basically, need to wait for 6 cycles in order for the microprocessor to receive the data from data memory.
-Assumption2: Instead of changing the clock speed to fit all instructions in a single-cycle, we have control circuits to deal with different clock cycles for each instruction for comparison purpose to other architectures. Namely, we need to spend the aforementioned clock cycles for each instruction.
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