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FPGA-Based Digital System Design

This document is for Coventry University students for their own use in completing their
assessed work for this module and should not be passed to third parties or posted on any
website. Any infringements of this rule should be reported to
facultyregistry.eec@coventry.ac.uk.
Faculty of Engineering, Environment and Computing
FPGA-Based Digital System Design
Assignment Brief

Module Title
FPGA-Based Digital System
Design
Group Sep 2020 Module Code
7067CEM
Coursework Title (e.g. CWK1)
Group Project
Hand out date:
23rd November 2020 (T11)
Lecturer
Dr. Arfan Ghani
Due date and time:
Date: 11th December 2020
Online: 18:00:00
Estimated Time (hrs):
25
Word Limit*: 2000 words group rport
Coursework type:
Group
% of Module Mark/
5 Credits
Submission arrangement online via Aula:
File types and method of recording:
Mark and Feedback date (DD/MM/YY): T16
Mark and Feedback method (e.g. in lecture, electronic via Aula): Aula
Module Learning Outcomes Assessed:
1. Model digital electronic functions for simulation, verification and synthesis using Hardware
Description Language such as VHDL.
2. Create test benches for the verification of digital design and systems employing VHDL.
3. Synthesise large scale digital systems for implementation on FPGA hardware making use of third
party intellectual property.
4. Apply contemporary computer aided design tools for digital system design and implementation.
Task and Mark distribution:
You should use Vivado as installed in Faculty computer rooms to complete this coursework OR free
version of the tool could be installed on your personal machines. The details of the software have
been provided on AULA. This package is available for free download from www.Xilinx.com –
registration and license agreement required.
You should submit your work electronically to the 7067CEM AULA site as a single pdf document
before 6 pm on the day of the deadline. Do not leave submission to the last minute. The file name for
your submission should be your student identification number with the extension .pdf. Note that
University installations of Microsoft Word include a pdf conversion utility.
Your document should be produced to the following specification – marks will be deducted if you do
not follow the instructions.
You should use this briefing document as a template.

This document is for Coventry University students for their own use in completing their
assessed work for this module and should not be passed to third parties or posted on any
website. Any infringements of this rule should be reported to
facultyregistry.eec@coventry.ac.uk.

Group Members:
Name SIDTask details:
Title: VHDL Implementation of Individually Addressable LED Drivers (4×4) Array
1. Project Aims
This project is related with the research field of image and vision engineering. It involves the design and
implementation of LED array drivers on hardware platform (simulations).
2. Project Tasks
Main tasks of the project are as under:
a. Design specification (15%)
b. Input image (alphabets) conversion into binary form (15%)
c. System Design (50%)
i. Level 0 (10%): Basic functional LED driver implementation (4 x 4 array) in VHDL with
character display;
ii. Level 1 (10%): testing level 0 with the test bench;
iii. Level 2 (10%): Analysis of multiple addressing modes (serial/parallel) with respect to
area (logic blocks), power consumption (dynamic) speed (access/refresh) and
scalability;
iv. Level 3 (10%): Using an IP core (could be MicroBlaze) to control LED matrix array.
v. Level 4 (10%): Complete design synthesis, evaluation and final simulations.
4. Final report (20%)

This document is for Coventry University students for their own use in completing their
assessed work for this module and should not be passed to third parties or posted on any
website. Any infringements of this rule should be reported to
facultyregistry.eec@coventry.ac.uk.

Background details:
Light Emitting Diodes are widely used for applications in imaging, medicine, and signalling (roads,
airports and advertising). It is relatively simple to drive LEDs individually. However, as the number of
LEDs increase, the amount of resources needed to operate these LEDs grow to an unsustainable level.
Hence, LEDs are often organized in matrices to make effective use of resources. Typically, in a matrix
the LEDS are arranged in rows and columns (see Fig. 1).
Fig. 1 (LED Matrix)
As shown in Fig. 1, each LED can be individually addressed by specifying its location in terms of rows (i)
and columns (j), Pixel P(i,j). For example, the LED on the top left is addressed by P(A,1), the line i=A and
column j=1.
Multiplexing is the technique used to make LED matrices work. By multiplexing, a single row or column
of the LED array is activated at any time. In this project, students are expected to work in small groups
(maximum 3 student in each group) and design/implement individually addressable LED drivers. The
system should include the conversion of small images (for example alphabets) into binary image,
develop state machine to control individual LEDs and display letter on the LED matrix.
Design space need to be explored such as optimised data path/control, access/refresh time, logic
utilisation (area), power consumption and speed.
Sub-level i, ii and iii: In order to score marks in this area, the design space needs to be explored in
terms of multiplexing schemes for multiple modes. The state machines should be clearly documented
alongside with quantitative analysis of performance in terms of speed (access/refresh), area (optimised
design) and power consumption.
Sub-level iv and v: Marks in this section will be awarded based on the evidence shown for simulated
design.
Testing: Test bench needs to be developed to show detailed simulated design where waveforms are
clearly annotated and commented.
Note: Please document your VHDL/C/C++ code, all simulation/synthesis result reports, state machine
transition diagrams, and data path and control. Please comment on the scalability and give suggestions
as to how the design could be optimised in future. It is also required that you submit a soft copy of your
VHDL code/ project files on AULA. Marks will be awarded based on the understanding and the quality
of project.

This document is for Coventry University students for their own use in completing their
assessed work for this module and should not be passed to third parties or posted on any
website. Any infringements of this rule should be reported to
facultyregistry.eec@coventry.ac.uk.

Notes:
1. You are expected to use the Coventry University APA style for referencing. For support and
advice on this students can contact Centre for Academic Writing (CAW).
2. Please notify your registry course support team and module leader for disability support.
3. Any student requiring an extension or deferral should follow the university process as outlined
here.
4. The University cannot take responsibility for any coursework lost or corrupted on disks, laptops
or personal computer. Students should therefore regularly back-up any work and are advised to
save it on the University system.
5. If there are technical or performance issues that prevent students submitting coursework
through the online coursework submission system on the day of a coursework deadline, an
appropriate extension to the coursework submission deadline will be agreed. This extension will
normally be 24 hours or the next working day if the deadline falls on a Friday or over the
weekend period. This will be communicated via your Module Leader.
6. *(ML’s delete if not applying to this assessment) Assignments that are more than 10% over the
word limit will result in a deduction of 10% of the mark i.e. a mark of 60% will lead to a reduction
of 6% to 54%. The word limit includes quotations, but excludes the bibliography, reference list
and tables.
7. You are encouraged to check the originality of your work by using the draft Turnitin links on Aula.
8. Collusion between students (where sections of your work are similar to the work submitted by
other students in this or previous module cohorts) is taken extremely seriously and will be
reported to the academic conduct panel. This applies to both courseworks and exam answers.
9. A marked difference between your writing style, knowledge and skill level demonstrated in class
discussion, any test conditions and that demonstrated in a coursework assignment may result in
you having to undertake a Viva Voce in order to prove the coursework assignment is entirely your
own work.
10. If you make use of the services of a proof reader in your work you must keep your original version
and make it available as a demonstration of your written efforts.
11. You must not submit work for assessment that you have already submitted (partially or in full),
either for your current course or for another qualification of this university, with the exception of
resits, where for the coursework, you maybe asked to rework and improve a previous attempt.
This requirement will be specifically detailed in your assignment brief or specific course or module
information. Where earlier work by you is citable, i.e. it has already been published/submitted,
you must reference it clearly. Identical pieces of work submitted concurrently may also be
considered to be self-plagiarism.

Mark allocation guidelines to students (to be edited by staff per assessment)

0-39 40-49 50-59 60-69 70+ 80+

This document is for Coventry University students for their own use in completing their
assessed work for this module and should not be passed to third parties or posted on any
website. Any infringements of this rule should be reported to
facultyregistry.eec@coventry.ac.uk.

Work mainly
incomplete
and /or
weaknesses in
most areas
Most elements
completed;
weaknesses
outweigh
strengths
Most elements
are strong,
minor
weaknesses
Strengths in all
elements
Most work
exceeds the
standard
expected
All work
substantially
exceeds the
standard
expected

This document is for Coventry University students for their own use in completing their assessed work for this module and should not be passed to third
parties or posted on any website. Any infringements of this rule should be reported to facultyregistry.eec@coventry.ac.uk.
Marking Rubric (To be edited by staff per each assessment)

GRADE ANSWER RELEVANCE ARGUMENT & COHERENCE EVIDENCE SUMMARY
First
≥70
Innovative response, answers the
question fully, addressing the learning
objectives of the assessment task.
Evidence of critical analysis, synthesis
and evaluation.
A clear, consistent in-depth critical and
evaluative argument, displaying the ability
to develop original ideas from a range of
sources. Engagement with theoretical
and conceptual analysis.
Wide range of appropriately supporting
evidence provided, going beyond the
recommended texts. Correctly
referenced.
An outstanding, well-structured and
appropriately referenced answer,
demonstrating a high degree of
understanding and critical analytic skills.
Upper Second
60-69
A very good attempt to address the
objectives of the assessment task with an
emphasis on those elements requiring
critical review.
A generally clear line of critical and
evaluative argument is presented.
Relationships between statements and
sections are easy to follow, and there is a
sound, coherent structure.
A very good range of relevant sources is
used in a largely consistent way as
supporting evidence. There is use of
some sources beyond recommended
texts. Correctly referenced in the main.
The answer demonstrates a very good
understanding of theories, concepts and
issues, with evidence of reading beyond
the recommended minimum. Well
organised and clearly written.
Lower Second
50-59
Competently addresses objectives, but
may contain errors or omissions and
critical discussion of issues may be
superficial or limited in places.
Some critical discussion, but the argument
is not always convincing, and the work is
descriptive in places, with over-reliance on
the work of others.
A range of relevant sources is used, but
the critical evaluation aspect is not fully
presented. There is limited use of sources
beyond the standard recommended
materials. Referencing is not always
correctly presented.
The answer demonstrates a good
understanding of some relevant
theories, concepts and issues, but there
are some errors and irrelevant material
included. The structure lacks clarity.
Third
40-49
Addresses most objectives of the
assessment task, with some notable
omissions. The structure is unclear in
parts, and there is limited analysis.
The work is descriptive with minimal
critical discussion and limited theoretical
engagement.
A limited range of relevant sources used
without appropriate presentation as
supporting or conflicting evidence coupled
with very limited critical analysis.
Referencing has some errors.
Some understanding is demonstrated but
is incomplete, and there is evidence of
limited research on the topic. Poor
structure and presentation, with few
and/or poorly presented references.
Fail
<40
Some deviation from the objectives of the
assessment task. May not consistently
address the assignment brief. At the
lower end fails to answer the question set
or address the learning outcomes. There
is minimal evidence of analysis or
evaluation.
Descriptive with no evidence of theoretical
engagement, critical discussion or
theoretical engagement. At the lower end
displays a minimal level of understanding.
Very limited use and application of
relevant sources as supporting evidence.
At the lower end demonstrates a lack of
real understanding. Poor presentation of
references.
Whilst some relevant material is present,
the level of understanding is poor with
limited evidence of wider reading. Poor
structure and poor presentation, including
referencing. At the lower end there is
evidence of a lack of comprehension,
resulting in an assignment that is well
below the required standard.
Late submission 0 0 0 0

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